Integrated circuits are typically designed to communicate signals with external devices through bonding pads on the periphery of the integrated circuit. Circuitry contained on the integrated circuit is designed to operate within predetermined voltage supply levels, which depend upon the process technology used, to produce the integrated circuit. In contrast, external circuitry does not necessarily operate within the same voltage limits as the circuitry on the integrated circuit. This presents a conflict which must be resolved in order for the integrated circuit to be as compatible as possible with external circuitry.
An example of such a situation occurs with an integrated circuit which is designed to receive signals according to the RS422 interface. This interface is defined in "EIA Standard RS422A," Electronics Industry Association, Dec. 1978. It is a differential, balanced voltage interface capable of high data rates over long distances. It can accommodate rates of 100 kilobaud over a distance of 4,000 feet, or rates of up to 10 megabaud. This high performance stems from the advantages of a balanced double input signal configuration which is isolated for ground noise currents. Because is it a differential interface, the RS422 interface is also immune to both fluctuating voltage potentials between system ground references and common mode electromagnetic interference.
As a differential interface standard, the RS422 interface will operate correctly as long as an appropriate differential voltage is maintained between the standard two input signal lines, regardless of the absolute voltage levels of those lines. However, due to the common mode voltage changes to which the two input voltages are susceptible, especially over long distances, the voltages on the signal lines according to an RS422 standard may be outside of the voltage range of the integrated circuit. Such voltages have the potential of damaging the chip by triggering "latch-up," as a result of forward-biasing the parasitic diodes at the input pads to the integrated circuit. This latchup phenomenon is described in "Latchup in CMOS Technology," by Ronald R. Troutman, Kluwer Publishers, 1986.
Several techniques may be used to protect the integrated circuit from latch-up damage while allowing it to continue operating. One technique might be to generate higher voltage supplies on the integrated circuit. This can be accomplished by incorporating a charge pump on the circuit. However, the supplies cannot be raised due to drain-to-source breakdown voltages, hot electron effects, and impact ionization problems.
Another approach to protect the integrated circuit is to use circuits that can tolerate signals larger than the supply voltages. This can be accomplished by increasing the thickness of the insulating layer on the MOS field effect transistors (MOSFETs) of the chip. Unfortunately, increasing the thickness of the gate layer decreases the operating speed of the MOSFET's circuitry.
A third technique to protect the integrated circuitry is to scale the signal voltages to be within the limits of the integrated circuits voltage supplies. This can be accomplished by dropping the large input voltages across resistors between the integrated circuits' input pads and the MOSFET circuitry of the chip.
The resistive layers available in digital MOS processes are polysilicon, a conductive "well," an active layer in the substrate, and an active layer in a conductive well. Until the recent introduction of silicide processing, polysilicon was useful as a resistive element. Silicide processing reduces the sheet resistance of polysilicon to improve the speed of the circuitry. Unfortunately, this also limits the use of polysilicon as a resistor because a much longer length of silicided polysilicon is required to produce a given resistance.
A "well" resistor is not usable in standard bulk complementary metal oxide semiconductor (CMOS) technology because the parasitic pn diode between the well and the substrate prevents signal excursions beyond one of the chip's voltage supplies. A resistor made by placing an active layer in the substrate has the same problem as the "well" resistor, as does a resistor made by placing an active layer in a well connected to a supply voltage.
Accordingly, it is desirable to produce a resistive element that can be used on integrated circuits containing CMOS circuitry without limiting the speed of the circuitry, while allowing the input voltages to fall outside of the range of the integrated circuits voltage supplies.